The tremendous progress in high performance Very-Large Scale Integrated (VLSI) circuit technology now allows several million transistors to be incorporated onto a single silicon chip with on-chip clock rates as high as 200 MegaHertz (MHz). By the end of the decade, the integration density for silicon Complementary Metal Oxide Semiconductor (CMOS) technology is expected to be over 20 million transistors with a projected on-chip clock rate of 500 MHz. The enormous bandwidth that will be available for computation and switching on a silicon integrated circuit will create a huge bottleneck for the Inputs and Outputs (I/Os) that serve as interconnects to the VLSI circuit. Currently, the most widely used interconnect technique involves placing the I/Os along the periphery of the integrated circuit. A simple perimeter-versus-area calculation shows that the number of transistors per I/O channel will continue to increase, leading to an I/O performance bottleneck. In practice, off-chip clock rates are usually much smaller that on-chip clock rates, increasing the demands placed on the I/Os even further. Thus, a means of incorporating high-performance I/Os in a silicon chip is needed to fully exploit the tremendous computational capabilities of current and future VLSI circuits.
Optical I/Os can overcome this bottleneck because of their greater bandwidth, immunity from crosstalk and signal interference. Additionally, optical I/Os can be fabricated in large, high density arrays. Optical I/Os have been used as interconnects for integrated circuits to form "smart pixels." An example of a smart pixel array is shown in FIG. 1. The array includes a plurality of individual smart pixels 2 arranged in a symmetric manner. Each smart pixel includes an electronic circuit cell 3, a photodetector 4 with an associated receiver circuit 5 and a modulator 6 with an associated modulator driver circuit 7. The circuit cell comprises related electronic circuitry that processes the electrical signal received at one or more of its inputs and produces an electrical signal at one or more of its outputs. The electronic circuit cell has a predefined number of electrical inputs and outputs. The particular nature of the circuit cell depends on the type of electrical processing it is to perform. Some common examples of a circuit cell include random-access memories, arithmetic logic units, and high-speed multipliers or even an entire VLSI chip. In the case of a conventional smart pixel array, the circuit cell is usually a simple logic circuit with about 100 transistors. The photodetector 4 and its associated receiver circuit 5 serve as the optical input that converts an optical input signal to an electrical input signal. The photodetector 4 first converts the optical input signal to a photocurrent. The receiver circuit 5 then converts the photocurrent to an appropriate voltage compatible for use as the electrical input to the circuit cell. The modulator 6 and its associated modulator driver circuit 7 serve as the optical output that converts an electrical output signal from the circuit cell to an optical output signal. The modulator driver circuit 7 receives the electrical output signal from the circuit cell 3 and converts it to a voltage that is applied to the modulator 6. The modulator 6 varies the intensity of an optical beam in proportion to the voltage applied to it. The optical beam thus modulated by the modulator 6 serves as the optical output signal. The photodetectors and modulators are typically reverse-biased diode devices.
The design of a smart pixel array proceeds as follows. First, the location of all the photodetectors and modulators on the entire integrated circuit is selected. The photodetectors and modulators are positioned so that they form a regular array. Such an arrangement is important because the optical input signals are usually generated by an external optical system that can most conveniently transmit the optical information to all the photodetectors as a series of parallel optical signals that are transmitted in a spatially symmetric manner. If the photodetectors were arranged in an irregular or asymmetric fashion, the complexity of the required optical system would be greatly increased. These same considerations apply to the modulators, which transmit the optical output signals to an external optical receiver that most conveniently receives the signals in a symmetric manner. After the location of the photodetectors and modulators have been determined, the layout of the entire electronic integrated circuit is performed. That is, the integrated circuit is partitioned into a series or array of circuit cells that in the case of smart pixels are referred to as pixels. Next, the particular location and size of each electronic component (e.g., transistor, capacitor and interconnection line) in a given pixel is determined. Since all the pixels in a smart pixel array are substantially identical, once the design of a single pixel have been completed, it may be replicated for the remaining pixels.
As detailed above, the electronic integrated circuit in a smart pixel array is not designed independently of the optical I/Os. That is, the smart pixel design process preselects the location of the photodetectors and modulators prior to designing the electronic integrated circuit. This places severe constraints on the design of the electronic integrated circuit, limiting the designer's flexibility in sizing and locating the transistors and interconnection lines. Thus, for example, the maximum level of complexity of each circuit cell (i.e., pixel) is typically dictated by the available area between the predetermined location of the photodetectors and modulators. Due to these constraints placed on the design of a smart pixel array, the circuit cells in the array are typically limited to low levels of complexity, are homogeneous relative to one another, and have limited electrical communication with one another.
Optical I/Os for integrated circuits other than those used in smart pixel arrays is problematic. In general, an integrated circuit contains numerous circuit cells that are highly complex and non-homogeneous in terms of both their function and in terms of the number of electronic components such as transistors and interconnects that they employ. As a result, the constraints imposed on electronic integrated circuits which are designed by the previously-described design procedure prevent such complex integrated circuits from being supplied with optical I/Os.